# Open Source Semiconductor Security Platform Development

**Funder:** EPSRC
**Budget:** Up to £240,000 (80% of FEC up to £300,000)
**Duration:** 12 months
**Application:** Single stage (details to be published on opening)
**Frequency:** One-off
**Eligible countries:** GB
**Official call:** https://www.ukri.org/opportunity/open-source-semiconductor-security-platform-development/
**Last updated:** 23 Aug 2026

## Eligibility & scope

UK-only call (national capability focus); EPSRC standard eligibility applies; project lead must be an existing employee of an eligible UK organisation. International collaborators included as project partners only — no international co-leads. Funds one-year research projects on semiconductor security (vulnerabilities, attacks, mitigations, security-aware EDA tools) to inform design of a BIST-funded open-source hardware security platform ahead of first tape-out.

## Summary

EPSRC funds one-year research projects on semiconductor security vulnerabilities, attacks, mitigations, and security-aware design tools to inform development of a BIST-backed open-source hardware security platform. The call is UK-only, with up to £240,000 per project (80% of eligible costs, capped at £300,000 FEC). This is a strategic, one-off opportunity for research teams to shape a national open-source hardware capability ahead of first silicon tape-out.

## Who should apply

- Researchers at eligible UK academic or research institutions in leadership roles
- Project leads already employed by the eligible organisation (not postdoctoral fellows or students)
- Teams with expertise in hardware security, EDA tools, BIST design, or vulnerability assessment
- Collaborative teams willing to partner with international experts (though project lead must be UK-based

## Key dates

- Single-stage application; full details and deadline to be published when the call opens
- 12-month project duration

## Tips for applicants

- This is a capacity-building call aligned to a BIST-funded platform rollout; frame your project as directly informing the open-source hardware design pipeline.
- International collaborators are welcome as co-investigators but cannot hold the project lead position, structure your team accordingly.
- The 80% FEC cap at £300k means budgets over £375k full cost will be scaled; keep project scope realistic within the £240k band.

## Frequently asked questions

### How much can I apply for in the EPSRC Semiconductor Security Platform call?

Up to £240,000 (80% of eligible full economic cost, with a ceiling at 80% of £300,000 FEC).

### Who can be the project lead on a semiconductor security platform grant?

An existing employee of an eligible UK research organisation; international researchers may participate as co-investigators but not as project lead.

### What should my semiconductor security project focus on?

Research on hardware vulnerabilities, attacks, mitigations, and security-aware EDA tools intended to inform the design of an open-source BIST-funded hardware security platform before tape-out.

### Is this call recurring or one-time?

This is a one-off funding call aligned to a specific national capability initiative, not an annual competition.

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Source: [The Great Grantsby](https://grantsby.eu/grants/epsrc-open-source-semiconductor-security-platform-develo-2026) — EU grant monitoring for academic researchers. Always verify details on the funder's website before applying.

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